The present invention is directed to a computer cache subsystem. More particularly, the present invention is directed to a cache subsystem that includes a tag RAM with a selection module for a variable width address field.
Most computer systems today include a cache subsystem in addition to a main memory. The main memory is typically populated with relatively slow access, low cost dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) while the cache subsystem is typically populated with a relatively small amount of high cost, fast access static random access memory (xe2x80x9cSRAMxe2x80x9d) that functions as cache memory. The cache subsystem stores copies of frequently accessed information read from the main memory by the computer system""s processor.
In a typical cache subsystem, a subset of the information from main memory is stored in cache memory in the form of memory lines. Each line is identified uniquely by its memory address, which is divided into a set portion and a tag portion. The set portion identifies the specific location or xe2x80x9csetxe2x80x9d in cache memory where the line must be stored. The tag portion identifies a line stored in cache memory. Tags are stored in a separate tag random access memory (xe2x80x9ctag RAMxe2x80x9d) within the cache subsystem.
The cache subsystem and main memory in a computer system are coupled to an address bus. This can be a shared or separate address bus. An address bus includes multiple address bus bits, referred to as the xe2x80x9caddress field.xe2x80x9d In the typical computer system, the size of the address field width coupled to the cache subsystem is fixed. During a cache subsystem operation, the address field received by the cache is partitioned into a tag field and a set field. The set field identifies a set location in the cache memory. The tag field is stored in the tag RAM and identifies which sets are stored in the cache.
Some computer systems allow the amount of cache memory in the cache subsystem to be variable. However, the cache subsystems in these computer systems only support a fixed address field width because of the design of their tag RAM. For example, in computer systems designed around some processors from Intel Corp. that have a fixed width 24 bit wide address field, the amount of cache memory in the level 2 (xe2x80x9cL2xe2x80x9d) cache subsystem can be either 256 KB or 512 KB. When the cache memory equals 256 KB, the tag field is fixed at 13 bits wide and the set field is fixed at 11 bits wide. When the cache memory equals 512 KB, the set field is increased to 12 bits, which, because the address field is fixed, requires the tag field to be decreased to 12 bits.
A problem with these known variable cache memory arrangements is that the tag RAM is not fully utilized. For example, because the tag field can be up to 13 bits wide, the physical size of the tag RAM must be at least 13 bits wide. However, when the tag field is reduced to 12 bits, portions of the 13 bit wide tag RAM are unused. Further, because the tag RAM only supports a fixed address field width, the maximum amount of addressable main memory available to the processor is also fixed (i.e., the maximum amount of addressable main memory equals 2(address field width)).
Based on the foregoing, there is a need for a cache subsystem that accommodates variable cache memory sizes and a variable width address field, while fully utilizing its tag RAM.
One embodiment of the present invention is a tag RAM coupled to an address bus adapted to carry a variable width address field. The tag RAM includes a memory section coupled to the address bus and a comparator coupled to the address bus and the memory section. The tag RAM further includes a selection module coupled to the address bus and coupled to the comparator.